1. Field of the Invention:
The invention relates to the field of nonvolatile memory devices and, in particular, to an apparatus and means for preventing the accidental erasure and programming of nonvolatile memory devices, and more particularly, to a circuit for protecting against the over-erasure and over-programming during a power up and power down sequence of electrically programmable and electrically erasable read-only memories (EEPROMs) and to electrically programmable read-only memories (EPROMs) having floating gates implemented in metal-oxide-semiconductor (MOS) technology.
2. Art Background:
The fabrication of nonvolatile memory devices such as electrically programmable read-only memories (EPROMs) utilizing metal-oxide-semiconductor (MOS) technology is well known in the prior art. These EPROMs employ memory cells utilizing floating gates which are generally formed from a polysilicon member completely surrounded by an insulator. Electrical charge is transferred into the floating gate using a variety of techniques such as avalanche injection, channel injection, Fowler-Nordheim tunneling, channel hot electron injection, etc. A variety of phenomena have been used to remove charge from the floating gates, including exposing the memory to ultraviolet radiation. The floating gate is programmed when the charge is stored in the floating gate. The cell is in an uprogrammed, or erase state when the floating gate is discharged.
Because of the complex and time-consuming procedures required to erase EPROMs, these devices have been used primarily in applications requiring read-only memories. Electrically programmable and electrically erasable read-only memories (EEPROMs) were developed to erase and to rewrite the memory devices on a byte-by-byte basis. These EEPROMs have also been referred to as electrically alterable read-only memory. Commercially available EEPROMs have generally used a thin oxide region to transfer the charge into and from a floating gate. In a typical memory, a two-transistor cell is used. For instance, U.S. Pat. No. 4,203,158 discloses the fabrication of such EEPROM cell. Further, U.S. Pat. No. 4,266,283 discloses the arrangement of EEPROMs into an array wherein X and Y select lines provided for the selection, programming, and reading of various EEPROM cells.
More recently, a new category of electrically erasable EPROMs has emerged and is sometimes referred to as "Flash" EPROMs or EEPROMs. In these memories, the entire array is simultaneously erased electrically. The cells themselves use only a single device per cell, and such cells are described in the pending application Ser. No. 892,446, filed Aug. 8, 1986, entitled "LOW VOLTAGE EEPROM CELL," which application is assigned to the assignee of the present invention. Flash memory devices combine the electrical erase capability of the EEPROMs with the simplicity, density and cast-effectiveness of EPROM cell layout. As such, modification of the EPROM cell replaces block UV-erasure with block electrical erasure while the device is still installed in the host system. Flash memory can also be randomly read or written. The present invention is directed towards the use of these cells as well as improvement thereon.
When a computer system to which a nonvolatile memory is coupled goes through a power up or power down transition, the system-level signals such as Vcc or Vpp are not guaranteed to be valid. Vcc is generally a 5 V supply for controlling the logic and the read mode of the nonvolatile memory device. Vpp is a 12 V supply for controlling the programming mode of the nonvolatile memory device. By power up transition, the present invention refers to the moment when the user starts the computer system. On the other hand, by power down transition, the present invention refers to the moment when the user turns off the computer system. In the past, users adhered to a power up and power down sequence in order to guarantee that the system-level signals such as Vcc and Vpp are valid. Failure to follow the power up or power down sequence exposes the nonvolatile memory devices to spurious system-level signal operations and result in data corruption or physical damage to the nonvolatile memory device. Data corruption arises because of over-programming, i.e., the application of high Vpp when the nonvolatile memory is not in a programming mode. Physical damage to the nonvolatile memory refers to another problem, specifically over-erasing. An over-erase condition arises because too much charge was removed from the floating gate, making the floating gate device "depletion-like." Unlike over-programming where the memory cells of the nonvolatile memory device is undamaged, an over-erase condition often results in permanent damage to the memory cells of the nonvolatile memory device.
The closest prior art known to applicant is a voltage lockout detector circuit disclosed in an article entitled "Control Logic and and Cell Design for a 4K NVRAM" IEEE Journal of Solid State Circuits, Volume SC-18, No. 5, October, 1983, pp. 529-530.